Scientific Computing on FPGAs
Field Programmable Gate Arrays (FPGAs) are a novel way of providing increased computing capacity using limited space and power. They can be hard-wired to carry out specific numerical algorithms and as such can be many times faster than using conventional CPUs. As leaders of the FPGA High-Performance Computing Alliance EPCC have developed an FPGA cluster, one of the largest parallel FPGA systems in the world.
Currently, programming these novel processors requires a high level of electrical engineering knowledge. The Scientific Computing on FPGAs activity will try to test the latest compiler tools for these processors to see if standard scientific computing kernels can be ported across to FPGAs by programmers, rather than electrical engineers.
Phase I
In Phase I an existing High Performance Computing benchmark, STREAM, was successfully ported onto a Xilinx Virtex-II Pro FPGA. The whole process was documented in order to evaluate the tools available and examine the performance of the FPGA. More information can be found in the presentation by PaulGraham given at the first edikt workshop with a further presentation given by Dr RobBaxter at the 4th edikt workshop.
The Phase I final report is available here (PDF).
The Phase I project members were CharakaPalansuriya, GeorgeBeckett, PaulGraham and JamesPerry.
Phase II
Phase II aims to take forwards the Phase I STREAM work and investigate programming the Virtex 4-based FHPCA supercomputer Maxwell. Maxwell comprises 64 FPGAs, bigger and more capable than those in the minisystem evaluated in Phase I. This phase of the work is co-sponsored by eDIKT and the HPCx Terascaling activity.
Phase II revolves around a number of hardware/compiler pairings to investigate not only the ease of use of FPGA programming tools but the efficiency of code they generate relative to software running on microprocessors. All together we plan to look at:
STREAMSinDIME-C on Nallatech H101 hardware
- STREAM in Handel-C on Alpha Data ADM-XRC-4FX hardware
- STREAM in the Xilinx CHiMPS compiler on Nallatech H101 hardware
- STREAM in the Xilinx CHiMPS compiler on Alpha Data ADM-XRC-4FX hardware
- STREAM in VHDL on H101
- STREAM in VHDL on ADM-XRC-4FX
The Phase II team is AdrianJackson, JamesPerry and RobBaxter.
Phase II talks and papers
Phase II also involves providing ongoing support for users of Maxwell and a continuing publications activity. Some recent papers and talks include:
Reconfigurable Systems Summer Institute 2007:
slides: RSSI-Jul07.ppt
paper: RSSI07-Maxwell.pdf
Adaptive Hardware and Systems 2007:
High Performance Reconfigurable Computing - the View from Edinburgh (invited keynote)
slides: AHS07-HPRC.ppt and paper: AHS07-HPRC.pdf
The FHPCA Parallel Toolkit (invited talk)
slides: AHS07-PTK.ppt and paper: AHS07-PTK.pdf
Maxwell - a 64 FPGA Supercomputer (invited talk)
slides: AHS07-Maxwell.ppt and paper: AHS07-Maxwell.pdf
Publications
See Publications